The AVSBus Slave IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The AVSBus Slave IIP can be implemented in any technology.
The Slave IIP core supports the AVSBus specification as defined in version 1.3.1 Part III of PMBus Bus Specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
The Slave IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Slave IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.