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The Interrupt controller IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SOC or FPGA development.The Interrupt controller IIP can be implemented in any technology.

The Interrupt controller IIP core supports the Interrupt controller specification. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

The Interrupt controller IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Interrupt controller IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.