The JESD207 RFIC IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The JESD207 RFIC IIP can be implemented in any technology.
The JESD207 RFIC IIP core supports the JESD207 specification. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
The JESD207 RFIC IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The JESD207 RFIC IIP is validated using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.