The LPC DEVICE IIP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The LPC DEVICE IIP can be implemented in any technology.
The LPC DEVICE IIP core supports the LPC v1.1 standard. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
The LPC DEVICE IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The LPC DEVICE IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.