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MIPI Soundwire Slave

The MIPI SOUNDWIRE SLAVE IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The MIPI SOUNDWIRE IIP can be implemented in any technology.

The MIPI SOUNDWIRE SLAVE IIP core supports the MIPI SOUNDWIRE 1.1x specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

The MIPI SOUNDWIRE SLAVE IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The MIPI SOUNDWIRE SLAVE IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.