The USB2.0 Hub IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The USB2.0 Hub IIP can be implemented in any technology.
The USB2.0 Hub IIP core supports the USB 2.0 Specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture – AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
The USB2.0 Hub IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The USB2.0 Hub IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.