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DFI LPDDR5 PHY

The DFI LPDDR5 PHY IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The DFI LPDDR5 PHY IIP can be implemented in any technology.

The DFI LPDDR5 PHY IIP core supports the LPDDR5 protocol standard of JESD209-5 specification and it is compatible with DFI-version 5.0 Compliant. DFI LPDDR5 PHY IIP also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, OCP, Wishbone, VCI, Avalon PLB, Wishbone or custom buses.

The DFI LPDDR5 PHY IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The DFI LPDDR5 PHYIIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.