The GDDR3 Controller IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The GDDR3Controller IIP can be implemented in any technology.
The GDDR3 Controller IIP core supports the protocol standard GDDR3 specification and is compatible with DFI-version 4.0 or 5.0 specification compliant. GDDR3 controller IIPalso supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
The GDDR3 Controller IIP is delivered in Verilog RTL that GDDR3 be implemented in an ASIC or FPGA. The GDDR3 Controller IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.