The LPDDR5 Controller IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The LPDDR5 Controller IIP can be implemented in any technology.
The LPDDR5 Controller IIP core supports the LPDDR5 protocol standard of JESD209-5 and JESD209-5A specification and is compatible with DFI-version 5.0 specification Compliant. LPDDR5 Controller IIP also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
The LPDDR5 Controller IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The LPDDR5 Controller IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.